Semiconductor manufacturers typically test and calibrate their products prior to being shipped, so that the shipped performance will meet performance specifications. This is of special relevance in “high speed” circuits, such as microprocessors, phase-locked loops, radio frequency circuits, where calibration can result in performance variation of over an order of magnitude.
One key calibration parameter is transistor gate delay. This parameter, which can vary from wafer to wafer as well as from die to die largely determines many important performance parameters of the chip. Hence, in the case of microprocessors, for example, the vendors typically need to be able to measure the gate delay of the various gates within the chip.
However, there are some problems associated with conventional technologies. For instance, gate transmission testers typically require extra equipment and chip space. This can be a significant problem when trying to reduce the amount of overhead required for efficient design.
Therefore, there is a need for a method and/or apparatus to determine gate delay parameters in a manner that addresses at least some of the concerns of conventional gate parameter testers.